ASIC Design and Synthesis:...
Vaibbhav Taraate
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BSV by Example
Kathy R Czeck,
Rishiyur S Nikhil
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High Level Synthesis of Asics...
David C Ku,
Giovanni Demicheli
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Transaction-level Modeling...
Frank Ghenassia (Editor)
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CMOS Cascade SIGMA-Delta...
Roc?o R?o Fernßndez,
Fernando Medeiro Hidalgo
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Physical Design Essentials:...
Khosrow Golshan
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Network Processor Design:...
Patrick Crowley (Editor),
Mark A Franklin (Editor)
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Appropriate Technology: Tools...
Barrett Hazeltine,
Lars Wanhammar
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Application-Specific...
Michael Smith
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Building Asips: The Mescal...
Matthias Gries,
Kurt Keutzer
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Practical Synthesis of High...
Emil S. Ochotta,
Tamal Mukherjee
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Verilog: Frequently Asked...
Shivakumar S. Chonnad,
Needamangalam B. Balachander
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Closing the Gap Between ASIC ...
David Chinnery,
Kurt Keutzer
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ASIC and FPGA Verification: A...
Richard Munden
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An ASIC Low Power Primer:...
Rakesh Chadha,
J Bhasker
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Reuse Methodology Manual for...
Michael Keating,
Pierre Bricaud
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Timing Verification of...
Farzad Nekoogar
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Hardware Implementation of...
Jean-Pierre DesChamps
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Power Management Integrated...
Amit Patra,
Shailendra Baranwal
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Reuse Methodology Manual for...
Pierre Bricaud
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Embedded DSP Processor Design...
Dake Liu
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Deep-Submicron CMOS ICS: From...
Harry Veendrick
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Network Processors:...
Panos C Lekkas
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Hdl Chip Design: A Practical...
Douglas J Smith
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