The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor ...
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The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. Audience: A reference work for graduate students, senior undergraduates, and researchers.
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Add this copy of Layout Optimization in VLSI Design to cart. $159.69, new condition, Sold by Ingram Customer Returns Center rated 5.0 out of 5 stars, ships from NV, USA, published 2010 by Springer-Verlag New York Inc..
Add this copy of Layout Optimization in VLSI Design to cart. $202.20, new condition, Sold by Ria Christie Books rated 5.0 out of 5 stars, ships from Uxbridge, MIDDLESEX, UNITED KINGDOM, published 2010 by Springer-Verlag New York Inc..
Add this copy of Layout Optimization in VLSI Design to cart. $159.69, new condition, Sold by Ingram Customer Returns Center rated 5.0 out of 5 stars, ships from NV, USA, published 2001 by Springer.
