Nano-CMOS Gate Dielectric Engineering

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According to Moore 's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. ...

Nano-CMOS Gate Dielectric Engineering 2011, CRC Press, Boca Raton, FL

ISBN-13: 9781439849590

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