Minimizing and Exploiting Leakage in VLSI Design

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This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage.

Minimizing and Exploiting Leakage in VLSI Design 2014, Springer, New York

ISBN-13: 9781489985293

2010 edition

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Minimizing and Exploiting Leakage in VLSI Design 2009, Springer, London, England

ISBN-13: 9781441909497

2010 edition

Hardcover

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