Low-power High-speed ADCs for Nanometer CMOS Integration

by

Write The First Customer Review

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0 ...

Low-Power High-Speed ADCs for Nanometer CMOS Integration 2010, Springer, Dordrecht

ISBN-13: 9789048178858

Paperback

Select
Low-Power High-Speed Adcs for Nanometer CMOS Integration 2008, Springer, Dordrecht, Netherlands

ISBN-13: 9781402084492

2008 edition

Hardcover

Select