Formal Semantics and Proof Techniques for Optimizing VHDL Models

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Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be ...

Formal Semantics and Proof Techniques for Optimizing VHDL Models 2012, Springer

ISBN-13: 9781461373315

Softcover Reprint of the Origi edition

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Formal Semantics and Proof Techniques for Optimizing VHDL Models 1998, Springer, Boston, MA

ISBN-13: 9780792383758

1999 edition

Hardcover

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