Cache and Interconnect Architectures in Multiprocessors

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Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 ...

Cache and Interconnect Architectures in Multiprocessors 2011, Springer

ISBN-13: 9781461288244

Softcover Reprint of the Origi edition

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Cache and Interconnect Architectures in Multiprocessors 1990, Springer, Boston, MA

ISBN-13: 9780792390749

1990 edition

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